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FPGA Design Using verilog with XILINX tools

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Training Module & Schedule
DAY - 1 DAY - 2 DAY - 3
FPGA FUNDAMENTALS & VERILOG BASICS
Introduction to FPGA
  1. ASIC vs FPGA vs CPLD
  2. FPGA architecture overview
  3. Types and applications of FPGA
  4. FPGA design flow
Xilinx Toolchain Overview
  1. Xilinx ISE / Vivado overview
  2. Project design flow using FPGA
  3. Project design flow using FPGA
  4. Introduction to ARTY-7 FPGA Board
Verilog Language Basics
  1. Verilog HDL overview
  2. Concurrency and delta delay
  3. Data types and operators
  4. Modules and port declarations
  5. Compiler directives and system tasks
  6. Blocking vs Non-blocking assignments
Practical Lab
  1. Tool installation and environment setup
  2. Creating first FPGA project
  3. Writing simple combinational Verilog design
  4. Simulation and waveform analysis
Hands-On Exercises
  1. Half Adder design
  2. Full Adder design
  3. Testbench creation and debugging
 4 Hours
VERILOG MODELING TECHNIQUES
Structural Modeling
  1. Gate primitives
  2. Delays in gate level modeling
  3. Arrays of instances
  4. Port connection rules
    • Ordered association
    • Named association
Dataflow Modeling
  1. Continuous assignment
  2. Delay modeling
  3. Operator precedence and usage
Behavioral Modeling
  1. Initial and always blocks
  2. Blocking vs non-blocking examples
  3. Conditional statements
  4. Sequential constructs
  5. Generate blocks
Tasks and Functions
  1. Task vs Function
  2. Writing reusable functions
  3. Modular design practices
Practical Lab
  1. Multiplexer design using structural modeling
  2. Behavioral modeling examples
  3. ALU design using functions
  4. Writing reusable testbenches
Hands-On Exercises
  1. Design and simulate MUX
  2. ALU behavioral design
  3. Functional verification using simulation
 6 Hours
FSM DESIGN, IP INTEGRATION & FPGA DEBUGGING
Finite State Machines
  1. FSM design concepts
  2. Moore vs Mealy machines
  3. FSM design methodology
  4. Verilog coding for FSMs
  5. Sequence detector example
FPGA Implementation Flow
  1. Synthesis and implementation
  2. Timing analysis basics
  3. Bitstream generation
  4. FPGA programming
IP Core Integration
  1. Using Vivado IP Catalog
  2. Core generation and configuration
  3. Instantiating IP cores in Verilog
  4. IP-based FPGA design flow
Practical Lab
  1. FSM design and simulation
Hands-On Exercises
  1. Sequence detector FSM implementation
 6 Hours

Eligibility

  • Basic understanding of Digital Logic Design (gates, flip-flops, FSMs).
  • Familiarity with Boolean algebra and combinational/sequential circuits.
  • Exposure to C or any programming language.
  • Knowledge of basic electronics and circuit simulation tools.
  • Interest in learning FPGA-based hardware design and HDL implementation.

Training Objectives

  • Introduce participants to FPGA architecture, toolchain, and design methodology.
  • Develop proficiency in Verilog HDL coding, simulation, and synthesis.
  • Enable participants to design and implement digital systems on FPGA hardware.
  • Familiarize learners with FSM design, IP core integration, and debugging tools.
  • Build capability to interface peripherals and work with ZYNQ SoC platforms.

Hardware Tools

FPGA Development Board: Xilinx ARTY-7 / ZYNQ SoC FPGA

Software Tools

Xilinx ISE / Vivado Design Suite (Evaluation Version)

Understand FPGA architecture and design flow using Xilinx tools.
Write, simulate, and synthesize Verilog HDL-based designs.
Implement combinational, sequential, and FSM circuits on FPGA boards.